Why, for over a decade, have all previous attempts at High Level Synthesis (HLS) failed - and continue to fail ?

a)      IP re-use provided enough productivity until now?
b)      No appreciation of differences between FPGA and ASIC HLS?
c)      Selective language support - HLS tools unable to truly support C, C++, System C, etc.?
d)      Limited language constructs in the 'supported ' language causing massive re-coding?
e)      Quality of RTL generated?
f)       RTL optimized for a single axis - area or performance?
g)      Power optimization not even considered?
h)      All of the above

The answer, of course, is h) All of the above.

All of the current HLS tools are limited by the era in which they were developed and are unable to truly solve all the above problems. In fact, it is difficult to tell the difference between the various vendors other than they are arguing over which language ought to be supported.

The Age of HLS is finally dawning....enabled by the right technology from AutoESL!

AutoESL is now selectively deploying a HLS solution that truly realizes the promise of ESL by solving all the above problems, in a manner that can be deployed beyond a few specialists. This advanced proprietary technology was nurtured, developed, and exclusively licensed from UCLA. AutoESL is currently previewing this solution at select leading edge system and semiconductor companies. 

Are you ready to enjoy the benefits of this breakthrough technology in your system, ASIC, or FPGA design?
If so, contact us at This e-mail address is being protected from spambots. You need JavaScript enabled to view it so we can help you plan to take advantage of what this dramatically new technology has to offer.